DRAM Architecture
A dynamic random access memory (DRAM) device consists of an arrangement of individual memory storage capacitors capable of storing digital data. The memory storage capacitors are also referred to as memory storage cells, memory cells, storage cells, and cells. The memory is often thought of as having two logic states, a high logic state and a low logic state. Each memory cell comprises a capacitor capable of holding a charge and a field effect transistor, hereinafter referred to as an access transistor, for accessing the capacitor charge. The charge is referred to as the digital data and can be either a high potential or a low potential corresponding to either the high logic state or the low logic state respectively. There are two options available in A DRAM memory, a bit of data may be stored in a selected cell in the write mode, or a bit of data may be retrieved from a selected cell in the read mode.